FPGA Mining Algorithms

Project Lead: Shahbaaz

Summary: Built low power consumption cryptocurrency mining solutions across numerous algorithms and FPGA boards.  

A Few Highlights

• RTL Design of SHA3 512/256 with clock cycles running at speeds of 550MHz
• RTL Design of SHA-256 (aka Bitcoin algorithm) with a hash at every single clock cycle running at 350MHz
• Designed RTL for Ethereum algorithm to work on FK33 board running at 400MHz